1. Field of the Invention
The present invention relates to the formation of structures in microelectronic devices such as integrated circuit devices. More particularly, the invention relates to the formation of vias, interconnect metallization and wiring lines using single and dual damascene processes.
2. Description of the Related Art
In the production of microelectronic devices, integrated circuits utilize multilevel wiring structures for interconnecting regions within devices and for interconnecting one or more devices within the integrated circuits. In forming such structures, it is conventional to provide first lower level wiring lines and then to form a second level wiring line in contact with the first level wiring lines. One or more interconnections are typically formed between the first and second level wiring lines or to other portions of the integrated circuit device.
One conventional method for forming a two level wiring structure is to first form a two level interconnect structure over a substrate. The surface of a substrate may be the surface of a silicon device structure or the surface of substrate may be an insulating layer. An oxide layer is typically deposited over the substrate by chemical vapor deposition. The first level interconnect structures are defined by a conventional photolithography process which forms openings through the oxide layer where the first level interconnects will be formed. Generally, the openings expose portions of conductors in the substrate to which interconnects are formed. The openings are filled with a metal interconnect such as titanium nitride or tungsten to form the interconnect and form a metal plug. The interconnect may be formed by CVD followed by an etchback or polishing process. Then a layer of metal such as aluminum is deposited over the surface of the oxide layer and over the metal plug to a thickness appropriate for second level wiring lines. The metal layer is then patterned into the second level wiring lines. The second level wiring lines are defined in a conventional photolithography process by providing a layer of photoresist over the metal layer, exposing the photoresist through a mask and removing portions of the exposed photoresist layer to form a photoresist etch mask. The portions of the metal layer exposed by openings in the photoresist mask are then removed by etching and the photoresist mask is removed by ashing. After the two level interconnect structure is formed, it is necessary to provide an intermetal dielectric (IMD) layer between the second level wiring lines and covering the second level wiring lines to accommodate further processing of the integrated circuit device. The intermetal dielectric layer might consist of one or more layers of oxide deposited by plasma enhanced chemical vapor deposition or other processes. The intermetal dielectric layer formed in this manner generally has an uneven surface topography. It is thus necessary to planarize the intermetal dielectric layer, using for example chemical mechanical polishing (CMP), to form a planarized intermetal dielectric layer.
The foregoing method of forming a the two level interconnect structure of has a variety of disadvantages. For those applications which use copper within the conductors or wiring lines, etching of the copper metal is very difficult since appropriate etching chemicals and techniques have not yet been identified. It is therefore desirable to utilize a method of forming wiring lines that does not rely on patterning a metal layer in a chemical etching process. Reduced device dimensions also introduce difficulties into the line formation method. Depositing metals into openings in dielectric layers and depositing dielectric materials into relatively narrow openings between metal lines are difficult processes that are subject to void formation and the trapping of impurities. This is particularly true as interconnects and wiring lines are made smaller and the spacing between wiring lines is made narrower. As such, the described prior process exhibits a high rate of defect formation which increases for smaller design rules. In addition, providing the necessary planar surface on the intermetal dielectric layer after completion of the two level interconnect structure requires additional processing steps. It is desirable whenever possible to reduce the number of processing steps required to form a device because reducing the number of processing steps shortens the time required to produce the device and because eliminating processing steps improves yields and so reduces costs. One alternative to the conventional interconnect formation process is the so called dual damascene process. Dual damascene processes are scaleable to smaller design rules and produce a planarized surface over the interconnect structure. Accordingly, a surface that is appropriate for further processing steps can be obtained using the dual damascene process in fewer process steps than discussed above. The dual damascene process begins with deposition of an oxide layer over a substrate. A relatively thin silicon nitride etch stop layer is deposited over the oxide layer for use in a subsequent etching step. A layer of intermetal dielectric is then deposited on the etch stop layer. Typically, the intermetal dielectric material is silicon oxide so that the underlying silicon nitride layer is an effective etch stop when openings for second level interconnects are provided in the oxide intermetal oxide layer. The thickness of the intermetal oxide layer is chosen to be that appropriate for the second level metal wiring lines.
A series of photolithography steps are performed to first define a pattern of the second level wiring lines and then to define the pattern of the interconnects within the first level of the interconnect structure. A mask is formed on the intermetal oxide layer where the mask includes a pattern of openings that correspond to the pattern of wiring lines desired for the second level wiring lines. Openings are then formed in the intermetal oxide layer by etching through the openings in the photoresist mask. The etching step proceeds first through the intermetal oxide layer to leave remaining portions of the intermetal oxide layer between the openings. This first etching steps stops on the silicon nitride layer, and then etching is performed aligned with the openings to etch through the silicon nitride layer, leaving remaining portions of the silicon nitride layer on either side of the openings. The photoresist mask is then removed by ashing. It is generally necessary for the width of the openings in the patterned intermetal oxide layer to be greater than the lithography resolution limit because further photolithography steps are necessary to define the interconnects of the first level. Forming the openings wider than the resolution limit provides greater process latitude for the steps used to form the first level interconnects.
A photoresist mask is formed over the device by conventional photolithography. Openings are provided in the mask that expose selected portions of the first oxide layer lying within the openings. Etching is performed on the first oxide layer exposed within the openings in the photoresist mask to define the pattern of interconnects that make up the first level of the interconnect structure. The photoresist mask is then removed by ashing. Next, a layer of metal is deposited over the device to fill the openings in the intermetal oxide layer and to fill the openings in the first oxide layer. Conventionally one overfills the openings in the intermetal oxide layer to ensure that the openings in both the intermetal oxide and the first oxide layer are completely filled. The excess metal is then removed, typically in a CMP process, to provide the second level metal wiring lines and first level interconnects of the two level interconnect structure. The final CMP step provides a planarized surface which is well suited to further processing steps. The dual damascene process provides several advantages over the conventional process, however, it is very demanding from a process technology point of view. In particular, the need for a tantalum nitride, tungsten nitride or titanium nitride diffusion barrier layer adds considerable unwanted thickness to the structure. It is therefore desirable to develop a damascene process that has wider process latitude and is more readily adapted to a high volume manufacturing process by either eliminating or reducing the thickness of such diffusion barrier layers. According to the one aspect of the invention, a nitride barrier layer may be eliminated by substituting a cured an upper portion of an applied dielectric layer such that is serves the purpose of the nitride layer. In another aspect of the invention, two dielectric layers are applied in juxtaposition to one another and the upper layer cured by electron beam exposure. The compositions of such dielectric layers are more compatible with one another, have reduced interlayer diffusion and hence can be thinner than nitride layers. Integrated circuits fabricated from thinner layers allow more features per device.